patpolt.blogg.se - Processor control

#Processor control series#

During Memory Read, the memory is required to indicate that Read Data is available on the Data Bus. Signals like Interrupts from IO Subsystem indicate the attention required from CPU. These indicate the state of CPU and Condition Codes (ZSOC) indicate the results of the previous operations within the CPU.Įxternal Control bus - The external sub-system status is communicated to the CPU over the Control Bus. The signals to be generated are written by the designer based on Instruction and the Datapath structure.įlags and Condition Codes - There are status flags like Trap, Interrupt, Parity, etc along with Condition Codes in the Processor Status register. Instruction register (IR) – IR holds the Op-code for current instruction and plays a major role in the definition of the micro-instructions required. More micro-operations per clock is feasible in a control step subject to (a) the pipelining and parallelism in the architecture and (b) that the micro-operations don’t conflict (for example, only one of them is allowed to output on the bus) with resource usage in that control step. The control unit issues one or more micro-operations per clock cycle. Processor Clock - The clock drives the Control unit and synchronizes the micro-operations. The output signals are generated based on the input conditions to the state machine. The Control Unit is a state machine that generates control signals based on certain inputs. Execution - Causing the performance of each micro-op.

#Processor control series#

Sequencing - Causing the CPU to step through a series of micro-operations.

Thus the control unit performs two tasks: Each control step corresponds to one clock cycle of the CPU. A set of control signals activates the micro-operations which have to be executed in a given control step. We have mentioned that the control unit is in charge of coordinating and synchronizing activities inside the CPU and also with the other subsystems of the computer. Generally, one needs to know what the datapath is currently doing, to tell it, what to do next. The appropriate control signals ensure that the data moves through the datapath in the right way during instruction execution.

Perform arithmetic or logical operations (ALU Operations part of any instruction)īased on the above datapath and the micro-steps, as above, the functions to be performed by the control unit are identified.

Data transfer from the external subsystems to Register (Load R4, LOC1, OUT #275).

Data transfer from Register to external subsystems like Memory or I/O (Ex: Store R4, LOC1, OUT #276).

Data transfer between registers (Ex: ADD R4, R5).The micro-operations to be performed by the processor can generally be classified as: Determine functions the control unit must perform (the Control signals required at timing states).Describe micro-operations processor performs (how the Datapath can best be used).Define basic elements of the processor (Datapath elements).Designing datapath gives a good idea of what control signals are needed. The datapath design precedes the Control Unit design. Figure 13.1 Typical Instruction Execution Flow Issues to be considered in the design of Control Unit Figure 13.1 explains the correlation from program to timing states during the execution flow. The period of these timing states corresponds to one CPU clock cycle or multiple clock cycles. Each micro-operation is executed in one timing state. The micro-operations are the functional or atomic operations of a Processor. Each of these macro steps has many sub operational steps called micro-operations. These macro steps are also called Machine Cycles. Also, Instruction Fetch and Operand Fetch are considered as two different macro steps. In some cases of Instruction, Interrupt recognition is an additional machine cycle. The number of such macro steps varies with different CPU design. Each instruction is executed with macro steps typically FETCH, DECODE, EXECUTE and RESULT WRITING.

Please recall the topic "Datapath Functioning" in chapter 12, wherein we had seen two examples demonstrating the micro-operations involved in instruction fetch and store operations.Ī program consists of a set of instructions. The number such micro-operations required to complete an instruction depends on the instruction and the datapath. Instruction execution is facilitated by a sequence of macro and micro-operations (steps) by the control unit. A Control unit is part of the CPU subsystem. These control signals facilitate flawless execution of instructions in CPU, handling of Interrupts and internal errors by CPU, communication over the internal bus(es) in CPU, communication over the external bus (external Datapath) to memory and IO subsystem. The purpose of the Control Unit is to generate control signals.